1. Field
Exemplary embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device which is capable of decreasing capacitance between a bit line and a storage node contact plug, and a method for manufacturing the same.
2. Description of the Related Art
Recently, as the degree of integration of a memory device increases, it may be considerably difficult to form a self-aligned contact (SAC) for a storage node contact plug (SNC) after forming a bit line with a stack structure. In a memory device of a 30 nm level or below, as a process margin decreases in such a way, the open area of a storage node contact hole may not be secured to thereby cause an SAC fail.
In order to cope with the features, a damascene bit line process has been introduced wherein, the damascene bit line process, a storage node contact plug is formed first and a bit line is then formed.
Specifically, in the damascene bit line process, two adjacent storage node contact plugs are formed to join together and are subsequently separated from each other through a damascene process. Thereafter, a bit line is formed to fill the inside of a damascene pattern. Due to this process, patterning may be easily performed in comparison with the case in which storage node contact plugs are individually formed. Also, there may be an advantage in terms of occurrence of an SAC fail in comparison with a process for subsequently forming the storage node contact plugs.
FIG. 1A is a cross-sectional view illustrating a conventional semiconductor device with a damascene bit line.
Referring to FIG. 1A, a plurality of active regions 13 are delimited by an isolation layer 12 in a semiconductor substrate 11. The respective active regions 13 are defined with bit line contact regions and storage node contact regions. Storage node contact plugs 15A and 15B are formed in the storage node contact regions of the active regions 13. Bit lines 16 are formed in the bit line contact regions of the active regions 13. The bit lines 16 are formed by being filled in the spaces defined between adjacent storage node contact plugs 15A and 15B (which are referred to as damascene patterns), and therefore, serve as damascene bit lines. Bit line spacers 17 are formed on both sidewalls of the bit lines 16 and on both sidewalls of the storage node contact plugs 15A and 15B. Further, bit line spacers 17 are formed between the storage node contact plugs 15A and 15B and the bit lines 16. The reference numeral 14 designates an interlayer dielectric or insulating layer, and the reference numeral 18 designates a bit line hard mask layer.
In the conventional semiconductor device constructed as described above, under the condition that the critical dimension (CD) of the bit line 16 is limited, bit line resistance (sheet resistance of a bit line per unit cell) and total bit line capacitance, that are in a trade-off relationship with respect to each other, should be simultaneously satisfied. However, in a semiconductor device of a 20 nm level or below, it may be difficult to simultaneously acquire two desirable values thereof.
In the structure mentioned above, in order to electrically completely isolate adjacent active regions 13, the bit lines 16 should have a depth that completely separates the storage node contact plugs 15A and 15B. Thus, when forming the damascene patterns for the bit lines 16, a portion of the isolation layer 12 should be etched as well. In this regard, if the critical dimension of the bit lines 16 increases, a contact resistance may increase since the contact area between the active regions 13 and the storage node contact plugs 15A and 15B may decrease. Therefore, considering overlay and CD variation, a securable CD of the bit lines 16 may further decrease.
FIG. 1B is a graph illustrating a relationship between bit line capacitance and bit line resistance depending upon a critical dimension difference in the conventional art. FIG. 1C is a perspective view illustrating the overlap area between a bit line and a storage node contact plug in the conventional art.
When describing a structural aspect with reference to FIG. 1B, if the critical dimension of the bit line 16 decreases (CD2>CD1, see {circle around (1)} of FIG. 1B), in order to obtain bit line resistance BLRs of a predetermined level, the height of the bit line 16 (a final bit line height after etch-back) should be increased. However, if the final bit line height is increased, an area (hereinafter, referred to as an ‘overlap area’) 100 (see FIG. 1C), through which the storage node contact plug 15B and the bit line 16 face each other, increases at the same rate. As a result, capacitance BLC between the bit line 16 and the storage node contact plug 15 may increases (see {circle around (2)} of FIG. 1B).
In an aspect of substance, development of a substance with low specific resistance as a metal layer used to form the bit line 16 is demanded, and a substance with a low dielectric constant is needed for the bit line spacers 17. In this regard, even when applying, to the spacers, a low resistance titanium nitride layer (TiN), a low resistance tungsten layer W and an oxide layer which have been developed so far, it may be difficult to satisfy the two properties described above.